`timescale 1ns / 1ps
/*
 * Copyright (c) 2020-2021, SERI Development Team
 *
 * SPDX-License-Identifier: Apache-2.0
 *
 * Change Logs:
 * Date             Author      Notes
 * 2021-10-29       Lyons       first version
 * 2022-04-04       Lyons       v2.0
 */

`ifdef TESTBENCH_VCS
`include "pa_chip_param.v"
`else
`include "../../rtl/pa_chip_param.v"
`endif

module core_tb(
    );


reg                             sys_clk;
reg                             sys_rst_n;

wire                            PAD_PA0;
wire                            PAD_PA1;
wire                            PAD_PA2;
wire                            PAD_PA3;
wire                            PAD_PA4;
wire                            PAD_PA5;
wire                            PAD_PA6;
wire                            PAD_PA7;
wire                            PAD_PA8;
wire                            PAD_PA9;
wire                            PAD_PA10;
wire                            PAD_PA11;
wire                            PAD_PA12;
wire                            PAD_PA13;
wire                            PAD_PA14;
wire                            PAD_PA15;

initial begin
`ifdef DUMP_VCD
    $dumpfile("wave.vcd");
    $dumpvars;
`endif
`ifdef DUMP_VPD
    $vcdplusfile("wave.vpd");
    $vcdpluson(0, core_tb);
`endif
end

wire                            clk_xtal;
wire                            clk_core;
wire                            rst_n;

assign clk_xtal = sys_clk;
assign rst_n = sys_rst_n;

pa_chip_top u_pa_chip_top (
    .clk_i                      (clk_xtal),
    .rst_n_i                    (rst_n),

    .clk_o                      (clk_core),

    .gpio_PA0                   (PAD_PA0),
    .gpio_PA1                   (PAD_PA1),
    .gpio_PA2                   (PAD_PA2),
    .gpio_PA3                   (PAD_PA3),
    .gpio_PA4                   (PAD_PA4),
    .gpio_PA5                   (PAD_PA5),
    .gpio_PA6                   (PAD_PA6),
    .gpio_PA7                   (PAD_PA7),
    .gpio_PA8                   (PAD_PA8),
    .gpio_PA9                   (PAD_PA9),
    .gpio_PA10                  (PAD_PA10),
    .gpio_PA11                  (PAD_PA11),
    .gpio_PA12                  (PAD_PA12),
    .gpio_PA13                  (PAD_PA13),
    .gpio_PA14                  (PAD_PA14),
    .gpio_PA15                  (PAD_PA15)
);

core_data_monitor_tb u_core_data_monitor_tb (
    .clk_i                      (clk_core),
    .rst_n_i                    (rst_n),

    .data_i                     (core_tb.u_pa_chip_top.u_pa_core_top.u_pa_core_rtu.u_pa_core_csr._mscratchcswl)
);

core_uart_monitor_tb u_core_uart_monitor_tb (
    .clk_i                      (clk_core),
    .rst_n_i                    (rst_n),

    .rxd                        (PAD_PA15),
    .txd                        ()
);

initial begin
    sys_clk = 1;
    sys_rst_n = 0;

`ifdef MEMORY_MODEL_REG
    $readmemh("image.pat", u_pa_chip_top.u_pa_perips_rom._ram);
`endif
`ifdef MEMORY_MODEL_BRAM
    
`endif
end

always begin
    @ (posedge sys_clk) sys_rst_n = 0;
    @ (posedge sys_clk) sys_rst_n = 1;

    while (1) begin
        @ (posedge sys_clk);
    end

    $stop();
end

always #((32'd1_000_000_000/`XTAL_FREQ_HZ)/2) sys_clk = ~sys_clk;

endmodule
